SRAM (“Static Random Access Memory”) type memory cells are static ram memories, that is to say memories that do not require periodic refreshing.
Such memory cells are constructed from a set of transistors.
A general concern in this field is how to reduce the size of the cells and how to reduce the leakage currents.
When an SRAM cell is fabricated on a bulk substrate, the size reduction results in a greater variability, which means that the dimensions of the transistors must not be reduced too much, and the read and write components must be separated in order to find an operating point.
This may entail increasing the number of transistors (thus increasing from 6 to 8, or even 10 transistors), with an attendant penalty in terms of surface area.
Moreover, on a “bulk” type substrate, the transistors have different dimensions, depending on their function within the cell (transfer, charge, conduction).
Authors have proposed using FD-SOI type transistors (an acronym standing for “Fully-Depleted SOI”, which describes a fully depleted structure produced on a silicon on insulator substrate) comprising a back control gate.
Reference in this respect can be made to the publications by Yamaoka et al. (“SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors”, IEEE Journal of Solid-State Circuits, Vol. 41, No 11, November 2006) and by Tsuchiya et al. (“Silicon on Thin BOX: A New Paradigm of the CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control”, IEEE 2004).
A conventional SRAM cell typically comprises six transistors, namely:
two access or transfer transistors: these are generally N channel field-effect transistors (NFETs), and
two charge transistors and two conduction transistors, linked in pairs so as to form two back-coupled inverters: the charge transistors are, in theory, P channel FET transistors (PFETs) and the conduction transistors are NFET transistors.
In the abovementioned publications, the back control gate, which is formed under the insulator, is used to control the operating conditions of the transistors more accurately.
The back control gate is a doped region formed under each transistor, each group of transistors and the underlying gate corresponding to an N+ or P+ type island being insulated from the others by so-called “STI” (“Shallow Trench Isolation”)
Thus, in an SRAM cell, the PFET transistors belong to one and the same island, while the NFET transistors are grouped in pairs (access transistors and conduction transistors respectively) in islands separated by the P region.
In practice, these two N regions are linked together at the periphery and to the other regions of the same type for the other columns. The same applies for the P region.
For N channel transistors, the region forming the back control gate is of P+ type, and is separated from the P type base substrate by a layer of N conductivity.
For the P channel transistors, the region forming the back control gate is of N+ type.
The article by Yamaoka et al. discloses a back control gate common to the two charge transistors, which are of P type, and a back control gate common to the access transistors and to the conduction transistors which are of N type.
In the article by Tsuchiya et al., the access transistors have a back control gate linked to ground and each pair formed by a charge transistor and a conduction transistor has a common back control gate.
However, in these devices, the back control gate simply comprises a well which is limited by the isolating trench.
Moreover, the choice of working in columns of wells does not favour the facilitation of the operating modes.
For example, the article by Yamaoka et al. describes N access transistors and N conduction transistors having the same back control gate such that their ratio remains constant regardless of the operating mode, thereby limiting the margin for improvement for the various functional modes.
Research is therefore focused on obviating the drawbacks of the existing devices and further reducing the dimensions of the SRAM-type memory cells, so as to conform roughly to Moore's law, while improving the performance levels of such cells.